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Entities

Entity and architecture declarations together define a design entity and its models of behavior. As we saw in the last section, entities are used to define the interface to a design. The example entity declaration of the last section consisted only of a port clause that defined the input and output signals of the design. However, an entity declaration may also contain other things. Among these is the generic clause. The generic clause is a very useful mechanism for designing generic designs that can be re-used. Re-use is important because it saves the time of designing similar parts and increases reliability.

The generic clause looks much like a port clause except that generics represent constants instead of dynamic signals. These constants are powerful because they can be given a different value every time the entity is used in a component instantiation.

Let's look at an example of a generic clause. The following declaration might be used for modeling an adder:

entity generic_adder is
  generic (width : natural;
           delay : time:=0ns);
  port (d1,d2 : in bit_vector (width-1 downto 0);
        sum : in bit_vector (width-1 downto 0)); 
end generic_adder;

The generic clause declares two constants, width and delay. The values of the constants will be defined when the entity is used for a component instantiation. So, rather than designing several adders with different word sizes we can use the same design. Once a generic library of parts has been established and used many times, the designer can be confident of the parts' reliability. If a generic design can be used from this library, instead of designing new parts all the time, then the result is increased reliability.

This example also illustrates three new types of objects. They are natural, time, and bit_vector. An object of the natural type may take on a value between 0 and 2147483647. The time type is used to specify time values that are written with a number followed by any of the standard abbreviations fs,ps,ns,us,ms, and sec. The :=0ns following the type name is called a default value. If the value is not specified when the entity is used for an instantiation then the default value is assumed. Since width does not have a default value, it must be given one when the design is used. Finally, the ports of this entity declaration use the bit_vector type. This is a one dimensional array of the bit type used in the last section. The (width-1 downto 0) part following the type name specifies the range of the array. The fact that we have used a constant generic has allowed us to delay supplying the actual range until we use the part, so that we can use it for more than one purpose. The range contains the downto keyword because the range is descending. The first bit in the vector is bit width-1 and the last bit is bit 0.

The following is a formal specification of how the port clause and generic clause may appear:

name-list : simple-name { "," simple-name }
mode : IN | INOUT | OUT
interface-signal : 
    [SIGNAL] name-list ":" [mode] subtype [BUS] [":=" expression] 
port-clause : 
    PORT "(" interface-signal {";" interface-signal} ")" ";" 
interface-constant :
    [CONSTANT] name-list ":" [IN] subtype [":=" expression] 
generic-clause : 
    GENERIC "(" interface-constant {";" interface-constant} ")" ";"

These specifications are called grammar rules. The first name on a line is the name of the rule being defined. This is followed by a colon and then the rule. The rule describes what must be present and what may appear optionally. Words in upper case are keywords that must appear literally. Likewise, symbols in double quotes must appear literally. Names in lower case are rules defined elsewhere that describes what should appear in their place. Anything in square brackets is optional and may or may not appear. Anything in braces may appear 0 or more times. In the above rules, name-list is a list of names separated by commas, subtype is a specification of the type, and expression is an expression of the named type. The type and expressions are described later. We have already seen some types such as bit, bit_vector, natural, and time. Actually, there is a difference between a type and a subtype that is discussed in the section on types and data objects. Notice that default expressions may also be used with port signals.

The entity declaration follows the rule:

entity-item_declarations : subprogram-declaration | 
  subprogram-prototype | type-declaration | subtype-declaration | 
  constant-declaration | signal-declaration | file-declaration | 
  alias-declaration | attribute-declaration | use-clause |
  attribute-specificiation | disconnection-specification
entity-statements : concurrent-assertion-statement |
    concurrent-procedure-call | process-statement
entity-declaration :
    ENTITY simple-name IS 
      [generic-clause] 
      [port-clause]
      {entity-item-declarations} 
    [BEGIN entity-statements] 
    END [simple-name] ";"

The list of items separated by | means exactly one of the items in the list may appear. If the simple name appears after the END keyword then it must be the same as the name of the entity.