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Component instantiation statements

In a purely structural view, a design would contain only component instantiation statements. They are the main constructs for specifying structure. The section on object declarations describes how a component could be declared. The declaration simply defines the part. The instantiation is the use of an actual instance of a part in the design. The syntax of the instantiation statement is:

generic-map : GENERIC MAP "(" association-list ")"
port-map : PORT MAP "(" association-list ")"
instantiation-statement :
  label ":" name [ generic-map ] [ port-map ] ";"

The instantiation must have a label so that it can be matched with a specification statement. The name is the name of the component being instantiated. The generic and port maps associate local signals with the formal port signals of the component being instantiated. The association is made with an association list the same way as was done for the procedure call statement.

With this definition, we now have defined all five of the necessary parts to define and instantiate a component. Before using a component, its interface is defined through the use of the component declaration. The instantiation statement specifies where to use the component and how to map declared signals to the formal signals of the defined interface in the component declaration. In order to model the component, the component specification statement specifies what entity and architecture should be used to model the operation of the component. The specification also specifies how to map the signals in the interface described by the component declaration to the signals in the entity interface. Finally, the entity and architecture actually describe how the component operates.

The following is a complete design file that uses component instantiations to build an adder.

-- declare an entity and architecture that models a full adder
entity full_adder is
  port (a,b : in bit;
        c_in : in bit :='0';
        s,c_out : out bit);
end full_adder;

architecture rtl of full_adder is
begin
  s<=a xor b xor c_in;
  c_out<=(a and b) or (a and c_in) or (b and c_in);
end rtl;

-- define an adder that uses the full adder as a component
entity adder is
  port (a,b : in bit_vector (1 downto 0);
        s : out bit_vector (1 downto 0));
end adder;

architecture structure of adder is
  -- declare a full adder component
  component fa
  port (x1,x2,c_in : in bit;
        out,c_out : out bit);
  end component;

  -- use the full_adder entity and its rtl architecture to model 
  --  the component fa for all instantiations
  for all:fa use entity full_adder(rtl)
    -- map x1 to a, x2 to b, c_in to c_in, out to s, 
    --  and c_out to c_out
    port map (x1,x2,c_in,out,c_out);

  -- declare an intermediate signal
  signal carry : bit;
begin
  -- instantiate a full adder for bit 0
  bit0: fa
    -- there is no association for c_in so it is open, its default
    --  value will be used
    port map (a(0),b(0),out=>s(0),c_out=>carry);

  -- instantiate a full adder for bit 1
  bit1: fa
    port map (a(1),b(1),carry,s(1),open);
end structure;