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Generate statements

The generate statement is used to iteratively or conditionally generate a block of concurrent statements. The syntax for the statement is:

generation-scheme : FOR parameter-specification |
    IF condition
generate-statement :
  [ label ":" ] generation-scheme GENERATE
    concurrent-statement-list
  END GENERATE [ label ] ";"

The condition of the parameter specification of the generation scheme must be static (i.e., contain only constant values). If the "if condition" scheme is used, then when the design is compiled, if that condition evaluates to true, then the concurrent statement list is compiled into the design and otherwise ignored. This form is useful for maintaining different versions that can be controlled by a global constant.

If the FOR scheme is used, the generate is much like a loop. Once for every value in the specified range, the specified constant name is set to that value and the concurrent statement list is compiled. This is very useful for generic designs. The following is a good example of how this might be used.

entity adder is 
  generic (width : natural);
  port (a,b : in bit_vector (width-1 downto 0);
        s : out bit_vector (width-1 downto 0);
        carry : out bit);
end adder;

architecture structure of adder is
  component fa
  port (x1,x2,c_in : in bit;
        out,c_out : out bit);
  end component;

  for all:fa use entity full_adder(rtl)
    port map (x1,x2,c_in,out,c_out);
  
  signal c : bit_vector (width downto 0);
begin
  c(0)<='0';

  bits: for n in 0 to width-1 generate
    bit_n: fa
      port map (a(n),b(n),c(n),s(n),c(n+1));
  end generate;

  carry<=c(width);
end structure;

This design has the same operation as if the instantiations were explicitly written for each bit, but this could not have been done without fixing the value of width.